-- EASE/HDL begin --------------------------------------------------------------
-- 
-- Architecture 'structure' of entity 'prescaler'.
-- 
--------------------------------------------------------------------------------
-- 
-- Copy of the interface declaration:
-- 
--   port(
--     clk     : in     std_logic;
--     clk_100 : out    std_logic;
--     clk_div : in     std_logic_vector(7 downto 0);
--     reset_n : in     std_logic);
-- 
-- EASE/HDL end ----------------------------------------------------------------

architecture structure of prescaler is
 
SIGNAL counter_dixmille : std_logic_vector(13 downto 0);
SIGNAL counter  : std_logic_vector(7 downto 0); 
 
BEGIN 
 
PROCESS(clk, reset_n) 
BEGIN 
  IF reset_n = '0' THEN 
    counter <= "00000001";
    counter_dixmille <= "10011100010000"; 
    clk_100     <= '0'; 
  ELSIF clk'EVENT AND clk = '1' THEN 
    IF counter = "00000000"AND counter_dixmille = "10011100010000" THEN  
       --counter_dixmille <= "10011100010000";
       counter <= clk_div; 
       clk_100     <= '1';
    else
    	clk_100 <= '0'; 
    END IF; 
    IF counter_dixmille = "00000000000000" THEN
      counter <= UNSIGNED(counter) - 1; 
      counter_dixmille <= "10011100010000";
    ELSE
      counter_dixmille <= UNSIGNED(counter_dixmille) - 1; 
    END IF; 
  END IF; 
END PROCESS; 
       
end architecture structure ; -- of prescaler
